Shallow trench isolation is a method of providing electrical isolation between adjacent semiconductor devices in an integrated semiconductor circuit, which is typically implemented in a semiconductor chip. The shallow trench isolation is employed in both bulk substrates and in semiconductor-on-insulator (SOI) substrates and provides more effective electrical isolation than LOCOS (local oxidation of silicon) insulation, while using smaller area of the semiconductor chip.
A shallow trench isolation structure comprises a dielectric material that laterally surrounds active areas (AA) of a semiconductor substrate comprising a semiconductor material, which is typically silicon. The shallow trench isolation structure is formed by first patterning a shallow trench that laterally surrounds the active area, followed by deposition of a dielectric material into the shallow trench and a subsequent planarization of the deposited dielectric material. The dielectric material is typically removed from above the active areas during the planarization step, and the remaining portions of the dielectric material within the shallow trench, which are typically contiguous throughout a large area of the semiconductor chip, constitute the shallow trench isolation structure. The dielectric material employed in the shallow trench isolation structure is typically silicon oxide, which may be deposited by various chemical vapor deposition (CVD) methods known in the art. Optionally a dielectric liner is formed on the sidewalls and bottom surfaces of the shallow trench prior to the deposition of the dielectric material. The dielectric liner may comprise the same material as the dielectric material deposited by CVD, or may comprise a different material such as silicon nitride or silicon oxynitride.
Referring to FIGS. 1A-1C, a prior art metal-oxide-semiconductor field effect transistor MOSFET) structure comprises a semiconductor substrate 108 containing a shallow trench isolation structure 120 that laterally surrounds an active area, which includes a source region 112, a drain region 114, and a portion of a semiconductor layer 110 located above a bottom surface of the shallow trench isolation structure 120. FIG. 1A is a top-down view, FIG. 1B is a vertical cross-sectional view along the plane B-B′, and FIG. 1C is a vertical cross-sectional view along the plane C-C′. The active area comprises the source region 112, the drain region 114, and the portion of the semiconductor layer above the level of the bottom surfaces of the shallow trench isolation structure 120. A gate electrode 132 separated from the semiconductor layer 110 by a gate dielectric straddles the boundaries between the active area and the shallow trench isolation structure. To insure that the gate electrode 132 fully overlaps the entire width of the active area even with overlay variations during manufacturing, the gate electrode 132 extends over the shallow trench isolation structure 120. Typically, the overextension of the gate electrode 132 is designed to be at least an overlay tolerance between the pattern for the gate electrode 132 and the active area (or the shallow trench isolation structure, which is the complement of the active area) to insure that the gate electrode 132 overlies the entire width of the active area. Gate spacers 140 are formed on the gate electrode 132 during the formation of the source region 112 and the drain region 114, which typically includes source and drain extension regions (not marked separately) that abut the gate dielectric 130 and deep source and drain regions (not marked separately) that extend deeper into the semiconductor substrate than the source and drain extension regions.
Charge carriers flow in the prior art MOSFET occurs from the source region 112 to the drain region 114. Specifically, electrons flow from the source region 112 to the drain region 114 for n-type MOSFETs, and holes flow from the source region 112 to the drain region 114 for p-type MOSFETs. Channel current Ic flows as the charge carriers, i.e., electrons or holes, flow in a channel located within the portion of the semiconductor layer 110 directly underneath the gate dielectric 130 in the direction of the arrow associated with the channel current Ic. Shallow trench isolation (STI) edge current Ie flows at the interfaces between the semiconductor layer 110 and the shallow trench isolation structure 120. The STI edge current is triggered by surface states generated by crystalline defects of the semiconductor layer 110 at the interface between the semiconductor layer 110 and the shallow trench isolation structure 120.
The STI edge current Ie may raise a significant performance issue due to its contribution to the total leakage current of the prior art MOSFET in an off-state. Particularly, the STI edge current Ie dominates the off-state leakage current in a narrow MOSFET, i.e., a MOSFET in which the width of the channel has a comparable dimension as the length of the channel, which is the distance between the source region 112 and the drain region 114. This is because the channel current Ic scales with the width of the channel, while the STI edge current Ie does not scale with the width of the channel, i.e., both a wide MOSFET and a narrow MOSFET have a pair of STI sidewalls that induce the STI edge current Ie. Thus, the STI edge current has a detrimental effect for narrow MOSFETs, such as MOSFETs in a static random access memory (SRAM) cell, that are employed in low leakage applications.
The surface states causing the STI edge current Ie can be caused by crystalline imperfections of the surface of the semiconductor layer 110 that laterally abut the shallow trench isolation structure, which is not aligned to any crystallographic orientations of the semiconductor layer 110 and thus necessarily contains crystallographic edges. Further, such a surface of the semiconductor layer also contains various surface defects 111 since chemicals employed in the etching step of the semiconductor layer 110 to form the shallow trenches form various point defects at the exposed sidewalls of the shallow trench, which become the surface of the semiconductor layer 110 that abut the shallow trench isolation structure. In addition, the dielectric material of the shallow trench isolation structure 120 induces surface states within the semiconductor layer 110 near the interface. Thus, surface states caused by various mechanisms including the surface 111 defects that occur within a depletion region the around the p-n junction between the semiconductor layer 110 and the drain 114 induce the STI edge current Ie. The depletion region is represented by the area of the semiconductor layer 110 and the drain region 114 that are bounded by the two broken lines in FIG. 1C.
In view of the above, there exists a need for a semiconductor structure that provides reduced off-state leakage current for a metal-oxide-semiconductor field effect transistor (MOSFET), and methods of manufacturing the same.
In particular, there exists a need for a semiconductor structure that eliminates or reduces an STI edge current especially for narrow field effect transistors and low power devices, and methods of manufacturing the same.